Apple M1/M2 chips feature ultra-fast 128KB L1 instruction cache and 12-way associative cache structures allowing execution of multiple instructions per clock cycle (IPC).
Visual representation of control loops, memory layout, and execution flow for CPU Pipelining & Cache Memory Hierarchy.
Fetches 32-bit instruction from memory address indicated by Program Counter (PC).
Control Unit decodes instruction opcode and reads register file operands.
Arithmetic Logic Unit (ALU) performs operation (ADD, SUB, AND, OR).
Reads/writes memory operand if instruction is LOAD or STORE.
Writes computed result back into destination register.
| Feature / Dimension | RISC (Reduced Instruction Set) | CISC (Complex Instruction Set) |
|---|---|---|
| Instruction Set | Simple, fixed-length instructions executing in 1 clock cycle (e.g. ARM, RISC-V) | Complex, variable-length multi-cycle instructions (e.g. x86_64) |
| Register Count | Large number of general-purpose registers | Fewer registers; relies on direct memory operands |
| Power Efficiency | High power efficiency (ideal for mobile & Apple Silicon) | Higher power consumption (traditionally desktop/servers) |
Detailed answers, interviewer pro tips, key takeaway summaries, and code examples formulated for technical rounds.
✅ Correction: Latency of 1 individual instruction remains the same; overall throughput across many instructions increases up to 5x.
Overlapped execution architecture boosting instruction throughput.